Domino logic stages are used in integrated circuits to provide high-speed logic functionality. In general, domino logic involves the charging of dynamic nodes during a precharge phase. Subsequently, during an evaluation phase, inputs are fed to the logic stage which may or may not evaluate to provide a path to the low voltage supply from one or more of the dynamic nodes. The dynamic nodes represent a logic high or a logic low depending on whether or not a path to the low voltage supply is formed. Generally, the dynamic node is connected to the input of a static gate (e.g., an inverter), and the output of the static gate is input to other dynamic gates. In this manner, logic can propagate through successive dynamic logic stages. Because high logic levels are precharged, the logic evaluation period is reduced in time. Active power in a domino or dynamic logic block can be reduced by slowing or stopping the clock, but leakage currents in the dynamic and static portions of the dynamic logic section will persist and contribute to power consumption.
One problem that can occur with domino logic is that current leakage can occur through connected logic gates during the precharge phase or other standby period. For example, where each dynamic node feeds an inverter, there can be leakage through transistors within the inverter during the period of time that the dynamic node is precharged high. With the input to the inverter at a logic high, leakage can occur, for example, through the inverter's P-channel transistor which is coupled to the high voltage supply. This leakage is particularly problematic where inverters or other logic gates employ low threshold voltage transistors in order to provide higher speed operation. The low threshold voltage transistors experience higher leakage current for a given gate voltage, thus they cause more of a problem.
One conventional solution to the problem of leakage current is to avoid using low threshold voltage transistors where problems occur. Thus, for example, a high threshold voltage P-channel transistor can be used in an inverter to avoid leakage current. Another conventional solution is to shut off power to an entire dynamic logic section including the dynamic gates and associated static logic gates to avoid any leakage current from that section. However, these conventional solutions suffer from problems in that it is undesirable to use high threshold voltage transistors, and it is undesirable to recharge all the dynamic nodes every time the power supply is turned back on. For example, if a dynamic node and the output of the associated static gate both go low in standby, one or the other will have to be recharged high in restart.